In high density memory systems, a typical non-volatile memory cell may include a metal-oxide semiconductor (MOS) FET transistor having a parameter, e.g., a transistor device threshold voltage, that may be varied for storing a desired information, e.g., by injecting charges into a floating gate or gate oxide. Accordingly, a current sunk by the memory cell in determining biasing states varies depending on the information stored therein. For example, to store information in a typical twin-transistor memory cell there is provided two different threshold voltage values for the cell, with each different threshold voltage value associated with a different logic or bit value.
Existing Twin Cell Multi-Time Programmable (MTP) Memory Architecture utilizes two transistors to store 1 bit of information uses a localized reference transistor per cell. Use of twin cells in an MTP memory open bitline architecture gives the highest density of about 1 Transistor per Bit but suffers from sensing margin problems. The MTP memory open bitline architecture (OBA) (1T cell for 1-bit) further needs a global reference wordline (WL).
FIG. 1A shows an exemplary non-volatile memory CMOS thin-oxide multi-time programmable memory (MTPM) twin cell array structure 10 which may be part of a memory device, or memory system. The MTPM twin cell array structure 10 consists of a plurality of memory cells 11 arranged by 2 dimensional matrix (e.g., m rows and n columns). For simplicity. FIG. 1A shows two columns (columns n=“k”, n=“l”) having two rows (m=i, and m=j), each column and row having two memory cells 11, however the actual memory array consists of significantly more cells 11.
Each of the plurality of twin-transistor memory cells 11 includes first and second transistors 15A, 15B for storing a single information bit. They each have a first terminal that are connected with a common node 13, coupling to a source line (SL) running in a grid (both horizontally and vertically) and coupling to other cells in the array 10. In this example, SL could either be coupled to a high voltage (Elevated Source Line (ESL)) or to 0V (Grounded Source Line (GSL)). The other terminal 14 of the first transistor 15A is coupled to the bitline true (e.g., BLkT in column k) and the other terminal 16 of the second transistor 15B is coupled to the bitline complement (e.g., BLkC in column k). Each BLkT and BLkC lines are shown running vertically, and respectively coupled to the twin-cells in same column in the array 10.
The same architecture is shown for the adjacent column “l”. Here, each Bitline BL/T and BL/C lines are shown running vertically, and respectively coupled to the twin-cells in its same column in the array 10.
The MTPM array 10 shown in FIG. 1A further includes two gate electrodes 20A, 20B respectively of the respective first and second transistors 15A, 15B which are connected to a common wordline (WL) conductor 50, running horizontally, and coupling to other cells in the same row in the array 10. For example, for row i of array 10, the twin-cell transistor electrodes 20A, 20B connect to Wordline WLi, and for row j, the twin-cell transistor electrodes connect to Wordline WLj.
As shown in FIG. 1, to store a bit value the cell 11 is programmed by increasing the transistor threshold voltage (Vt) of one of the twin transistors 15A and 15B. More specifically, the transistor undergoes a Vt shift when it is programmed. For example, when the 15A transistor is intended to be programmed, it is subjected to a high gate, or WL voltage (e.g., about 2.0 to 2.2V), and high SL voltage (e.g., about 1.5V to 1.8V), the BLT grounded (e.g. BLKt=0V), for a few milliseconds. This induces a Vt shift from its nominal value to a higher value due to BTI (Bias temperature instability) and HCI (hot carrier injection) effects. In this example, a first transistor, e.g., device 15A is shown exhibiting a first threshold voltage (Vt), e.g., its native Vt or initial value, and the second transistor, e.g., device 15B is programmed to exhibit an induced second threshold voltage, e.g., a Vt+shift (added) voltage. However, the VT states of the first and second transistors are interchangeable.
As shown in FIG. 2, the memory cell is configured in a twin-cell architecture similar to FIG. 1, but with two different Vt types (LVT and HVT) for the transistors in the twin-cell. This ensures a default state to be built in the cell. To store the opposite bit value, the transistor with lower Vt (LVT) is programmed so as to raise its Vt higher than that of the HVT transistor. The HVT transistor in this twin-cell acts like a localized reference.
A plurality of memory cells may be interconnected by SLs, BLs and gate lines to form a memory array. The cell selection for read/write is made by turning on the appropriate WL and BL with the voltage levels as shown in FIG. 1B. Thus, each cell pair may be separately programmed to have a Vt shift induced in either the True or the Complement transistor of the twin-cell.
As known, a threshold voltage Vt is the minimum gate voltage that is needed to be applied to turn on a transistor. The transistor undergoes a Vt shift when it is programmed. Typical Vt values may be about 0.25V to 0.3V. When the transistor is subjected to a high gate voltage (e.g., about 2.0 V to 2.2V), and high SL voltage (e.g., ˜1.5V-1.8V), with BL grounded, for a few milliseconds (i.e. when it is programmed), its Vt gets shifted from its nominal value to a higher value (e.g., about 0.45 V to 0.5V) due to BTI (Bias temperature instability) and HCI (hot carrier injection) effects.
For a program operation, an input digital data signal Din represents a programmable bit value to be written to the target memory cell 10 by controlling application of a WL voltage, a BLT voltage a BLC voltage, and an SL voltage to the cell transistors 15A, 15B. That is, write circuit drivers may be implemented to generate and apply programming voltages for bitline true (BLT) and bitline complement (BLC) conductors for writing a bit voltage value to the cells 15A, 15B. The target cell is accessed, e.g., via a voltage provided on the wordline WL 50 corresponding to a row of the memory cell, and bit cell voltage values are written to the T or C cell by applying appropriate voltages to the BLT and BLC terminals corresponding to a selected column (complementary lines) of the target memory cell 10. For example the target multi-time programmable bit cell programming voltages generated are applied to WL, BLT, SL and BLC.
When no WL signal is applied, or the voltage applied to WL is 0V, the MOS transistors 15A, 15B do not conduct, resulting in retaining their programmed states. Combinations of voltages can be applied to the first terminal, second terminal and gate terminals of the memory cell 10 to program, inhibit program, read and erase the logic state stored by the MOS transistors.
FIG. 1B shows a chart 35 explaining different modes of operation of the multi-time programmable memory array 10 of FIG. 1A including example voltages at the terminals of the cell transistors 15A, 15B that provide cell states including stand-by, write (program), read and erase (reset) operations.
These are: 1) a standby state when respective BLT and BLC terminals 14, 16 are floating with a wordline WL of 0.0 Volts applied to the gates of each transistor in the twin-cell 15B, 15A; 2) a write state, e.g., when the respective BLT terminal 14 is at 0 Volts and BLC terminal 16 is at about 1.7 Volts with a wordline WL of about 2.2 Volts applied to the gates of each transistor 15B, 15A and SL voltage of 1.7V; however, the voltages on BLT and BLC could be swapped to store a different logic value in the cell; 3) a read state when each respective BLT terminal and BLC terminal voltage values are such that a voltage delta between BLT and BLC proportional to the Vt shift in the cell is produced, and a wordline WL of 1.0 Volt (VDD) is applied to the gates of each transistor 15B, 15A in the twin-cell and SL of 1V is applied; and 4) an erase state, e.g., when the respective BLT terminal 14 is at 1.7 Volts and BLC terminal 16 is at 0.0 Volts with a wordline WL of −1.0 Volts applied to the gates of each complementary transistor 15B, 15A, as shown in FIG. 1A and FIG. 1B.
Referring to FIG. 1A, generally, in electronic circuits having such bit memory array 10, a sense amplifier circuit (not shown) is provided for obtaining a stored bit value, i.e., perform a memory read operation. Typically, the sense amplifier senses whether the T (true) or C (complement) transistor is programmed (Vt shifted). Such sense amplifier circuit reads a selected bit cell BLT voltage and BLC voltage value at respective BLT terminal 14 and BLC terminal 16 conductors for cells selected by an applied WL voltage, and as selected by a respective corresponding column select transistors (not shown) to select the corresponding target cell via a corresponding select signal and/or a select signal for complementary signals. The column select signals are the same for one pair of BLT and BLC conductors.
In the read operation, the differential voltage between BLT and BLC is amplified to appropriate logic levels using a sense amplifier. For example, the read state of about 0.5 volts (500 mV) for BLC (15A native state, or no Vt shift state) and the read state of about 0.3 volts (300 mV) for BLT (15B programmed state, or Vt shift state). This results in a 0.2V (200 mV) differential voltage built between BLT and BLC are shown in FIG. 1B at 36 for the sensing of BLT programmed state.
The use of a twin-transistor cell for storing a single information bit, shown in FIG. 1A has been proposed for non-volatile memories to reduce sensitivity to device variation.
For non-volatile twin cell memories which have write and effective erase conditions, multiple write cycles is easily achieved.
However, it would be highly desirable to provide a memory cell solution that improves the density of such non-volatile memory.